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From CompArch

A vector is a 1 dimensional array of data elements, V[0]..V[N-1]], where N is the vector length.

Packed Vector

A packed vector is a vector that contains packed data.

Typically, a packed vector register or memory location is characterized by having a fixed number of bits, e.g.

• 64 bits for Intel MMX, one of the first packed vector instruction set extensions.
• 128 bits for Intel SSE.
• 256 bits for Intel AVX
• 512 bits for Intel LRBNI

This fixed number of bits may be treated as vectors of several different data types, where the data types may have several different bit widths. The number of vector elements in such a packed vector is typically RegBits/DataElementBits, e.g.:

• a 64 bit register or location may be
  • 8 x 8b bytes (signed or unsigned)
  • 4 x 16b
  • 2 x 32b
  • possibly a single 64b value, scalar

Such a 64b packed value may be considered to be

• an 8 element vector of 8b values
  • V8b[0] = V[0:7], V8b[1]=V[8:15] ... V8b[7]=V[56:63]
• a 4 element vector of 16b values
  • V16b[0] = V[0:15], V16b[1]=V[16:31] ... V16b[3]=V[48:63]

and so on.

It is usual for the 32 or 64 bit data values to be considered as signed or unsigned integers, or as floating point. Similarly, 16b and 8b values are often signed and unsigned integers. Less common, but increasingly, 16b floating point (FP16) is found. Even 8b floating point. And various forms of fixed point, in addition to the integers.

Similarly

• a 512 bit register or location may be
  • 64 x 8b bytes
  • 32 x 16b
  • 16 x 32b
  • 4 x 64b

It is much less common, but keeping with the spirit, to have 128b, 256b, or 512b data elements or scalars.

I.e. I contend that the fundamental property of a packed vector is that as many of the data elements are crammed together as possible, that they each correspond to bit positions of the overall value. And consequently that the vector length varies according to the width of the data elements. Frequently the data elements of different sizes are overlaid and may be freely mixed:

I.e. V8b[0],V8b[1] = V16b[0] = V[0:15]

More generally, we can talk about packed vectors that are not in fixed size registers or memory locations. These would basically amount to have little or no padding between data elements.

However, such variable length packed vectors (both in bits and in number of elements) somewhat defeat the whole reason for doing packed vectors: the realization that an ALU of a given width (in bits) can fairly easily be adapted to perform packed vector operations on packed vectors whose data elements are of several different widths.

Non-packed Vectors

An example of a non-packed vector might be a machine that has, e.g.

• vector registers of length 16
• each vector element being 64 bits wide
• capable of holding one and only one data element in each vector element
  • e.g. an 8b element being zero or sign extended to the full 64 bits
  • similarly for 16b and 32b data elements
  • only a 64b data item making good use of all of the bits in a vector element.