$

• $
• $$
• $$$

A

• ABS
• ABSDIFF
• ALU
• ARF
• ASR
• Absolute value (ABS)
• Active register file (ARF)
• Address Generation Unit
• Address Generation Unit (AGU)
• Arithmetic-logic unit (ALU)

B

• BKM
• BMM
• BMM (Bit Matrix Multiply)
• BTB
• BTB (Branch Target Buffer)
• BTB (branch target buffer)
• BTBs and Indirect Branch Predictors are Branch Target Predictors
• BY$ (bypass cache)
• Bit matrix multiply (BMM)
• Branch Target Buffer (BTB)

C

• CAM
• CAM (Content Addressable Memory)
• CAS
• CAS (compare and swap)
• CISC
• CISC (Complex Instruction Set Computer)
• CISC (Complicated Instruction Set Computer)
• CMT
• COW
• CPI
• CRC
• Coherent Instructions Multiple Threads (CIMT)
• Coherent instruction data multithreading (CIDMT)
• Coherent multithreading (CMT)
• Common subexpression elimination (CSE)
• Complex Instruction Set Computer (CISC)
• Complicated Instruction Set Computer (CISC)
• Content Addressable Memory (CAM)

D

• D$
• D1$
• D2$
• DFA
• DFS
• DIMM
• DIMT
• DMT
• DRAM
• DSP
• DVFS
• DVS
• Data-flow Analyzer (DFA) (Intel simulator)
• DfX
• Dynamic Implementation Verification Architecture (DIVA)
• Dynamic multithreading (DMT)

E

• ECC
• ECC (Error Correcting Code)
• EDC
• EDRAM
• EU
• Error Correcting Code
• Error Correcting Code (ECC)
• Error correcting code (ECC)
• Execute Instruction In Memory

E cont.

• Execute Instruction In Memory (XMEM)
• Execute Instruction In Register (XREG)
• Execute Instruction in Register or Memory (XREG or XMEM)

F

• FADD
• FADD (floating point add instruction)
• FLC
• FMA (floating point multiply add)
• FMUL
• FMUL (Floating Point Multiply)
• FP16 (16-bit floating point format)
• FP7
• FP8
• FPGA
• FRC
• FSM
• Field programmable gate array (FPGA)
• Floating Point Multiply
• Floating Point Multiply (FMUL)
• Floating point add instruction (FADD)
• Functional redundancy checking (FRC)
• Future file (FF)

G

• GPR
• GPR (General Purpose Register)
• GPU
• General Purpose Register (GPR)
• Graphics Processor Unit (GPU)

H

• HT
• HT - ambiguous acronym
• HaRRM
• Hyperthreading (HT)

I

• I$
• I1$
• I2$
• ILP
• IMT (deprecated ambiguous acronym)
• IP
• IPC
• ISA
• Implicit multithreading (IMT)
• Instruction Set Architecture (ISA)

L

• L0
• L0$
• L1
• L1$
• L2
• L2$
• L3
• L3$
• LBA
• LBCA
• LBuA
• LIM
• LIM (Logic In Memory)
• LIMS
• LIMS (Logic in Memory System)
• LL-SC
• LLC
• LNS
• LNS (logarithmic number system)
• LSB
• LSQ
• Least significant bit (LSB)
• Ln
• LnM (Logic near Memory) deprecated
• Load-linked / store-conditional (LL/SC)
• Load-linked/store-conditional (LL/SC)

L cont.

• Log-based architecture (LBA)
• Log-based microarchitecture (LBuA)
• Logarithmic number system (LNS)

M

• MESI
• MIMD
• MLC
• MLC (Mid Level Cache)
• MLP
• MLP (memory level parallelism)
• MMIO
• MMX
• MOB
• MOV
• MP
• MSB
• MT
• Memory mapped I/O (MMIO)
• Move instruction (MOV)

N

• N-Instructions Multiple Threads (NIMT)
• NEGABS
• NEGABSDIFF
• NIMT
• NVRAM
• Negative absolute value (NEGABS)

O

• Out-of-order (OOO)
• Outer cache
• Outermost cache

P

• PCM
• PCM (Phase Change Memory)
• PGAS
• PHT
• PIC
• PIM
• PIM (Processing in Memory)
• PIMS
• PIMS (Processing in Memory System)
• PIO
• PIO (Programmed I/O)
• POPCNT
• PRF
• PSAD
• PnM (Processor (or Processing) near Memory) deprecated
• Population count (POPCNT)
• Position Independent Code (PIC)
• Program counter (PC)

Q

• QMR
• Quad module redundancy (QMR)

R

• RAM
• RAS
• RAT
• RAT (register alias table)
• RC
• RF$
• RF$ (register file cache)
• RISC
• RISC (Reduced Instruction Set Computer)
• RMW
• RRF
• RS
• Reduced instuction set computer (RISC)
• Reliability, availability, serviceability (RAS)
• Reverse instructions

S

• SAD
• SIMD
• SMT
• SNAD