Andy Glew's comp-arch.net wiki, http://semipublic.comp-arch.net
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comp-arch.net wiki on hold from October 17, 2011
What is a "bus"?
In computers, a bus is usually a set of wires, to which are attached multiple sender and receiver devices. Usually a bus is bidirectional: most of the devices can both send and receive.
E.g. a processor may be attached to a bus, which also connects to memory (DRAM) and peripheral I/O devices. Often, in older systems, the CPU processor was the only bus master, the only device capable of initiating transactions; the other devices were slaves. In more modern systems there may be bus mastering I/O devices. In multiprocessor systems there may be multiple masters.
A slightly older term for "bus" refers to a collection of wires running together, typically parallel to each other, without reference to electrical connectivity.
Over the years, more and more buses have been replaced, or evolved into, point-to-point interconnection fabrics. for example, the PCI bus evolved into PCIe (PCI Express), which is a point-to-point interconnection fabric. Strictly speaking PCIe is not a bus; but nevertheless many people, including the PCI SIG itself, occasionally refer to PCIe as a bus.
What is a "buss"?
Circa the 1980s (when I was in undergrad) certain pedantic engineers tried to promote use of the term "buss" for electrical and computer buses. Although occasionally still encountered, it is not common.
When is a bus not a bus?
The definition of "bus" as having more than one sender, and/or more than one receiver, is most common, and is distinct from point-to-point interconnections that have only a single sender and receiver. However, in the late 1990s and 2000s point-to-point interconnects became more common, and often replaced interconnects that had previously been buses. The term "bus" came to be applied to these new interconnections.
E.g. the original PCI was an electrical bus, with multiple senders and receivers. PCIe (PCI express) cinsists of point to point links. Yet people (and companies such as Intel) often refer to PCIe as a bus.
In particular, a star configuration, where multiple point to point links connect devices to a switch, is in many ways equivalent to a bus.
More general topologies of point-to-point links such as meshes may be referred to as interconnection fabrics.
Multistage hierarchical networks of muxes serve to create unidirectional multiple sender single receiver busses. Multistage hierarchical networks of switche serve to create unidirectional single writer multiple receiver busses. Or simply splitters, devices that drive the same signal on multiple outputs.
Unidirectional, point-to-point, link:
Sender | V +--------------------+ | V Receiver
Bus with multiple bidirectional attachments
P0 P1 P2 ^ ^ ^ | | | V V V +-----+----+
Bus with multiple senders and receivers
P0 P1 P2 | | | V V V +-----+----+-------------+-----+-----+ | | | V V V R0 R1 R2
Bus with a single sender and multiple receivers, aka a "unidirectional bus":
P0 | V +------------------------+-----+-----+ | | | V V V R0 R1 R2
Bus with multiple senders and a single receiver. This is arguably also a "unidirectional bus", although more people disagree:
P0 P1 P2 | | | V V V +-----+----+-------------+ | V R2
Address and Data Buses
Many systems combine separate bus for address and data into a single logical structure, often called simply "the bus". (Other systems have a single set of wires that carry both address and data.)
E.g. below we depict both address and data for reads
P0 ^ | | V outgoing read address | +------------------------+-----+-----+ | | | | | V V V | M0 M1 M2 | | | | | V V V +---------------------------+-----+-----+ incoming read data
and for writes
P0 | | | V outgoing read address | +------------------------+-----+-----+ | | | | | V V V | M0 M1 M2 | ^ ^ ^ | | | | +---------------------------+-----+-----+ outgoing write data
Arguably all of the buses above are unidirectional: data flows in only one direction on each, from processor to memory for address and write data, and from memory to processor on read data. The former is single writer; the latter is multiple sender, single receiver.
All of the above - separate read and write data busses, plus possibly a single addrss bus for both reads and writes, or separate address busses for reads and writes - may be combined, But it is more complicated than I want to draw with ascii art.